Silicon Devices (UK) Limited: IP Cells for Analog, RF ASICs and Modules - SDL: Providers of medium volume microelectronic Analog and RF Transceivers

IP cells

Cell Name	Sub-Cell	Shortform Spec	IP Available	SW tool or file type
		1.8V < Vdd < 5.6V Idd = 17.Iref 1MHz @ Iref=1uA Area=0.1mmsq in 0.35um CMOS	Design Note Schematic Test Bench Layout Model	MS Word WinLASI WinSPICE3 GDSII SPICE
Comparator			Design Note Schematic Test Bench Layout Model
Bandgap	OPAMP		Design Note Schematic Test Bench Layout Model
			Design Note Schematic Test Bench Layout Model
Crystal Oscillator	ESDPAD		Design Note Schematic Test Bench Layout Model
			Design Note Schematic Test Bench Layout Model
UpMix	VREF		Design Note Schematic Test Bench Layout Model
DnMix	VREF		Design Note Schematic Test Bench Layout Model
LPF			Design Note Schematic Test Bench Layout Model
	VREF ESDPAD		Design Note Schematic Test Bench Layout Model
AnalogLib	All Cells		Design Note Schematic Test Bench Layout Model
ATCXO

IP Cells are provided "as is" no warrantee is implied, nor given. Email us to register interest, request porting to other feature size CMOS technologies, to request file reformatting for simulation or layout in other tools.

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Delivering Mixed Signal and Full-Custom Analogue/RF IC Innovation from Concept to Production

Registered Office: Edwards House, 42-46 Bond Street, Southampton, Hampshire SO14 5QA United Kingdom.