VCO modelling and simulation in WinSPICE3.

This note shows how a simple VCO model maybe created, then simulated to show its functionality as an FM modulator using a "random data" digital baseband signal, moving it to a "wanted" carrier frequency.  The companion netlist  implements a relatively simple test-bench  in a readily available SPICE simulator by using a few simple mathematical formulae. 

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Simulation of VCOs in SPICE can be problematic, particularly if you are trying to create a behavioural model of a VCO.  The method used at Silicon Devices is based on the double integrator approach taken in "Phase Locked Loop Models: Making a VCO"  which was an IntuSoft Newsletter from April 1988, and was based on I. M. Filanovsky's method first published in his paper "A sinusoidal VCO with control of frequency and amplitude" published in the IEEE Proceedings of the Midwest Symposium on Circuits and Systems, 1989, pp446-449.

To adapt his method for use in WinSPICE3 we use a second order polynomial statement within the voltage controlled current sources to create a two input multiplier.  These VCCS's  charge ideal capacitors forming a double integrator.  Their netlist form is as follows:

***************************************************************************
*    out+ out- order   NC1+ NC1- NC2+ NC2- p0+p1f1+p2f2+p3f1^2+p4f1f2+....
  G1 Int1 gnd POLY(2)  Int2 gnd  con1  gnd  0  0    0    0      1
* C1 = 1/(2*PI*abs(Kv))
  C1 Int1 gnd 3.183u IC=0

*    out+ out- order   NC1+ NC1- NC2+ NC2- p0+p1f1+p2f2+p3f1^2+p4f1f2+....
  G2 Int2 gnd POLY(2)  Int1 gnd  con1  gnd  0  0    0    0     -1
* C2 = 1/(2*PI*abs(Kv))
  C2 Int2 gnd 3.183u IC=Vm
***************************************************************************

The control range for this type of oscillator is centered around 0Hz, so must be offset to Fo to model a real VCO, which is done by applying an offset voltage to the VCO's voltage control input.  The output amplitude is set by applying an "initial condition" (starting voltage) to one of the integrator capacitors, which will be the peak of the output sinusoid.  Here we have chosen the "sine" (or "Q") output, by setting the initial condition of C2 to 1Volt.  Kv is the VCO sensitivity (in Hz/V).  The full schematic for the Basic VCO model is as follows:

Setting the magnitude (Vm in netlist in Zip file) to minus the common mode output voltage (cm in diagram above) will minimize dv/dt start-up transients (and possible convergence issues).  The transient simulation's minimum time-step should be set fine enough to prevent magnitude decrease over time due to "numerical leakage" in the simulator.  Very high value resistors are added across the control input and integrator outputs to assist with convergence.  The full netlist  is given in FMmod2.mod in FMmod.zip.  It should be noted that this model may only be used in the time domain.

The Basic VCO model alone is probably not much use as looking at plots of the output sinusoid from the time domain model can be pretty intensive and difficult to interpret; it would be more meaningful to be able to look at the the frequency domain.  By recalling that the frequency domain is an integration of the time domain (and with a little bit of thought) we can come up with what might be called a "modulation meter". 

Kiranon and Wardkein published a paper titled "A Novel FM Demodulation Scheme" in the IEEE Transactions on Consumer Electronics Vol 41 Nov 1995 which outlined how this might be done, however their prime method used differentiators which can cause convergence issues when simulated in SPICE (due to large dV/dT at "startup").  By noting that either an integrator or a differentiator can be used to demodulate FM, we have implemented the integrator approach as suggested by Figure 2 of Kiranon and Wardein's paper. To reliably produce such an FM demodulator in a simulator such as WinSPICE takes a few tricks, not least of which is to produce a reliable square root function that will converge under all conditions and with near zero inputs.  To avoid this issue, we choose to implement root(x) as a graphical function, rather than a circuit element in the netlist. 

The input conditioning circuit takes the form of:

*** Simplified Deviation Meter ********************************************
*** Calculate Cint3=Cint2=Cint1=Cint0=(2*PI*fc)^-1 at fc (=125k)
*** Values given are for Fc=125k. Remember to enter Vcm to offset Fm:

Vcm V 0 1.5

Gint0 int0 0 Fm V -1.4142
Cint0 int0 0 1.2732u IC=0
Rint0 int0 0 1
Gint1 int1 0 int0 0 -1.4142
Cint1 int1 0 1.2732u IC=0
Rint1 int1 0 1
Eint1 g2 0 int1 0 1

Gint2 int2 0 g2 0 -1.4142
Cint2 int2 0 1.2732u IC=0
Rint2 int2 0 1
Gint3 int3 0 int2 0 -1.4142
Cint3 int3 0 1.2732u IC=0
Rint3 int3 0 1
Eint3 g3 0 int3 0 1
***************************************************************************

which in schematic form looks like:

The four integrator capacitors need to be set to 1/(2*PI*fc) where fc is the unmodulated carrier frequency (our example uses 125kHz).  Input common mode voltage must be removed from the input signal.  This form of the deviation meter will only be accurate for 1V equal mark space (ie sine-wave) inputs only.  It is possible to filter and condition the input signal to work on any input wave shape, but that will have to be the subject of another note.   (contact Silicon Devices to find out how!)

Once we have the two integrated outputs (g2 and g3) we can calculate the modulation as:

dFc = abs((g2^2-g3*fm))^0.5

which is with the WinSPICE3 plot statement written:

plot 2-(abs(((v(g2)-0)^2)-(v(g3)-0)*(v(Out)-0)))^0.5

Remember to subtract Vcm from g2, g3 & Out before calculating the result (the "0" in the above plot statement should be replaced by the common mode voltage if it was not removed before the input conditioning circuit).  In practice, it will be found a more accurate is achieved if the input DC common-mode is removed before the input conditioning and filtering, rather than in the plot statement, particularly for small modulation excursions with respect to the unmodulated carrier frequency.

The calculated output should then appear as follows when scaled by the unmodulated carrier frequency (125kHz):

We see that the output of the VCO is stepping up an down in frequency by +25kHz with some overshoot which is caused by the 2600Hz LC filter we chose to use in our netlist (see FMmodTest.cir in FMmod.zip) to emulate the behaviour of the VCO in a PLL.

For digital modulation applied to an FM modulator (ie a VCO) it would be more convenient to see the output as an "eye diagram" rather than a series of up-down transitions as in the plot above.  This may be achieved by producing a sawtooth ramp synchronized to the TIME variable (ie an oscilloscope sweep) by use of the atan() function as in the EDN Design Idea "Simulation technique emulates oscilloscope" by Alan Wolke [date unknown] as follows:

sweep* (atan(tan(PI(TIME/sweep * delay/sweep - 0.5))))/PI +0.5)

where "TIME" is SPICE's internal time variable, "sweep" is the time across which the waveform repeats, "delay" is the  initial delay  time before the waveform becomes repetitive, and PI is 3.1415926... as usual and for some versions of SPICE will need to be declared as a variable in the .PARAM line.  The above expression can be implemented in WinSPICE3 as:

plot v(data) vs 1m*(atan(tan(PI*(time/1m-0.25m/1m-0.5)))/PI+0.5)

By adjusting sweep and delay (values of 1m and 0.25m substituted in above plot expression) a plot like the following can be produced from the above demodulated stream:

Once we have an eye diagram like this, we  can see "data-dependent jitter" as in the small shifts in the above waveform due to the memory effect of the LC filter mentioned above.  For SPICE descriptions of real circuitry, this can be much worse than the ideal models we are using here to demonstrate the technique.

To complete the simulations required to assess basic VCO performance, we should look at the modulated spectrum of the VCO which can be done very simply in WinSPICE3 by use of the spectrum command in conjunction with the linearise command:

*** Plot Modulator Spectrum:
    linearize
***    startf stopf  stepf vector
***         |    |   |     |
      spec 256 250k 256 v(Fm)
    plot db(v(Fm)) ylimit -100 20

This will give an output after quite a period due to the FFT processing overhead.  It looks like this:

We see a spread in power over a wide band-width (the original unmodulated carrier is at 0dBV and 125kHz) note the small peaks in power at 100kHz and 150kHz which is due to the length of time the VCO output spends at these frequencies with respect to the times it spends at other frequencies; we also see how the power is spread outside the intended +25kHz deviation by the filter overshoot.

In this note, we have seen how we may create a simple VCO model, then simulate its functionality to quite a complex level using a relatively simple test-bench in a readily available SPICE simulator by implementing a few simple mathematical formulae.

The test-bench used in the above examples maybe downloaded at FMmod.zip.  You may also wish to contact  Technical@SiliconDevices.com  for an updated copy of the testbench which is subject to continuous development when simulating our IPcells throughout their design cycle.  If you have any questions, comments, feedback, or simply wish to explore VCO modelling further you may contact the author. 

Thank you for making the time to read this note; there are other notes in this series at:  Scattering Parameter Simulation in WinSPICE3.    Mixer Gain Simulation in WinSPICE3.   Also, if you have an interest in mathematical models for Phase-Locked Loop transient behaviour, or the prediction of PLL Phase-Noise performance, or the estimatation Phase-Frequency Detector Spurii in Charge-pumped Phase-Locked Loops, then we have a 77 page Design Note on "PLL System Design" available on-request.

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