Silicon Devices Circuit Resources: Scattering Parameter Simulation in SPICE - SDL: Providers of medium volume microelectronic Analog and RF Transceivers

Scattering Parameter Simulation in WinSPICE3.

In this note we outline one of the ways we at Silicon Devices simulate scattering parameters using WinSPICE3, a generic net-list driven linear and non-linear SPICE simulator. The netlists accompanying this note (available from our website) may easily be modified for use in other SPICE simulators by virtue of the use of generalized primitive functions in the netlist. Node names are meaningful easing the writing of the mathematical functions in WinSPICE3's graphical post-processor which minimizes the simulator's calculation overhead. The example netlist with this note reproduces scattering parameter plots like those to be found in some component manufacturers' datasheets.

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One of the basic bench test tools for any serious RF measurement is the Vector Network Analyser, which typically produces a circular plot presenting the scattering parameters (input and output reflection coefficients and forward and reverse transmission coefficients, based on incident transmitted and reflective power waves) on a complex plane known as a "Smith Chart". Basic texts on RF design deal with the mathematical derivation of these and Hasler dealt with implementing a basic scattering parameter test set in single ended form in his note titled "Use Inexpensive Spice Files for s-parameter Simulation" [R J Hasler, Microwaves & RF, May 1993, pp210-213]. Here we will concentrate on modifying Hasler's testbench to the more useful "balanced" form.

With reference to the full schematic for the balanced input/output "Vector Network Analyser" model, following, we see that the split source E1a/E1b and split source resistance R1p/R1n convert the single ended input to a balanced input. The input port common-mode bias is provided by Vdc1 and Rcm1. Usually Vdc1 is set to 0V and Rcm1 is set to a very high value (1E12) to prevent it loading either of the input ports, P1p/P1n. E2c/E2d, R2p/R2n, Vdc2 and Rcm2 fulfill a similar role for the output port P2p/P2n. By reducing Rcm1 to a low value, Vdc1 acts as the power source for an input "Bias-T" for a balanced input device. Similarly Rcm2 and Vdc2 can act as a bias-tee for the output port. To allow us to calculate the scattering parameters correctly, the isolated loops containing Rz1 with Iz1 and Rz2 with Iz1 allow us to pass the parameter Zo1 and Zo2 into the graphical post processor for carrying out scattering parameter conversions to other parameter sets; for example impedance parameters to determine input and output impedances for the device under test (DUT).

The combination of G11 with R11, G12 with R12, G21 with R21 and G22 with R22 allow us to parameterize the port impedances to correctly calculate the scattering parameter set when the port impedances are unequal. The WinSPICE3 netlist for the balanced form of a Vector Network Analyser (VNA) as shown in the above diagram is as follows:

********************************* Testbench *******************************
* Parameter direction:   V1 ... AC 1 = forward      V2 ... AC 1 = reverse
* Mixed Port Impedance: R12 = SQRT(Zo2/Zo1)        R21 = SQRT(Zo1/Zo2)
*                        R1p = R1n = Zo1/2          R2p R2n = Zo2/2
* Bias Tee: enable Vdc & Rcm
* Requires WinSpice3 V1.05.02 VCCS of the form:
* G Out+ Out- In+ In- {Value}
* Beware of setting Rcm1 or Rcm2 to a low value as they load their port
**************************************************************************
.PARAM Zs1=50 Zs2=50 PI=3.1415926
.PARAM R1cm=1E12 V1bias=0 R2cm=1E12 V2bias=0
************************ Vector Network Analyser *************************
Rcm1 cm1 dc1 {R1cm}
Vdc1 dc1 0   DC {V1bias}
VS1 SOU 0   DC 0 AC 1
R1p A   P1p    {Zs1/2}
R1n F   P1n    {Zs1/2}
E1a A   cm1 SOU 0   0.5
E1b cm1 F   SOU 0   0.5
G11 Inp 0   P1p P1n -2
R11 Inp 0           1
E11 S11 0   Inp SOU 1
G12 S12 0   P1p P1n -2
R12 S12 0    {SQRT(Zs2/Zs1)}
Iz1 Zo1 0 DC -1 AC -1
Rz1 Zo1 0    {Zs1}
Rcm2 cm2 dc2 {R2cm}
Vdc2 dc2 0   DC {V2bias}
VS2 LOA 0     DC 0 AC 0
R2p H   P2p    {Zs2/2}
R2n J   P2n    {Zs2/2}
E2c H   cm2 LOA 0   0.5
E2d cm2 J   LOA 0   0.5
G22 Out 0   P2p P2n -2
R22 Out 0           1
E22 S22 0   Out LOA 1
G21 S21 0   P2p P2n -2
R21 S21 0    {SQRT(Zs1/Zs2)}
Iz2 Zo2 0 DC -1 AC -1
Rz2 Zo2 0    {Zs2}
****************************** End of VNA ********************************

Having created the VNA netlist, we need to control the direction of signal flow to correctly plot the scattering parameters; either VS1 or VS1 should be active during a simulation, not both. WinSPICE3 is powerful for this type of simulation script control and allows us to simulate twice; alternately with each source whilst plotting the voltage at node S11 and S21 with VS1 active and nodes S12 and S22 with VS2 active. By plotting the real and imaginary parts of S11 and S22 on a log frequency x ordinate we should see something like the following:

WinSPICE3 has an internal command which allows us to plot these parameters on a complex x-y plane as a "Smith Chart" thus:

Once we can correctly plot a Smith Chart, we can go on to calculate input and output impedance by implementing the expressions needed from the scattering parameters in WinSPICE3's graphical post-processor (that is, enter the appropriate equations). The resistive or real part of the input impedance can be calculated with:

Rin = Zo1(Re((1+S11) / (1-S11))

which in WinSPICE3 plot syntax is:

ac1.v(Zo1)*real((1+ac1.v(S11))/(1-ac1.v(S11)))

where " ac1." means the first AC simulation (see the netlist with this note for clarification) when the input voltage source AC1 is active. A similar equation is written for the output resistance:

ac2.v(Zo2)*real((1+ac2.v(S22))/(1-ac2.v(S22)))

where "ac2." means the second AV simulation (where AC2 is active). The input and output reactance is found by altering "real" to "imaginary". The output plot should look something like this:

We see that the input and output reactance is negative (capacative) for this example. We can now see the utility of naming critical node with parameter names, allowing the transformation equations to be entered directly into the netlist.

Forward and reverse gain can be calculated with:

MAG = 20*log(S21) ANG = 180/PI*atan(imag(S21)/real(S21))
MAG = 20*log(S12) ANG = 180/PI*atan(imag(S12)/real(S12))

With AC1 active and AC2 active respectively. The output plot will look like this:

We can also calculate "unilateral transducer gain" for a "Device under test" with:

Gum = 10*log(abs(S21)^2/((1-abs(S11)^2)*(1-abs(S22)^2)))

which uses results from both simulations, resulting in a plot lke this:

In the examples above, we used a NPN RF transistor, for which we need a model file for the DUT; which is included in the example netlist we have provided with this note, being the BFR93AW from Philips. Correctly biasing a transistor DUT requires a a "dummy" or "replica" device biased at the required current and voltage level which is then used to bias the DUT through the VNA ports thus:

Notice that this is only possible in a simulation testbench and cannot be implemented practically due to mis-matches between the replica and the DUT. A one micro-ohm resitor is added into each device arm in the netlist (but not drawn in schematic above) to allow the correct naming and to prevent convergence problems. Large value Inductors are also added into the netlist across the VNA ports to ensure that both devices see the same DC bias.

In this note, we have seen how we may create a "balanced" VNA model, then simulate scattering parameters for a commercially available active device using a simple test-bench in a readily available SPICE simulator, by implementing a few simple mathematical formulae along with published device model libraries.

The test-bench used in the above examples maybe downloaded at VNAtest.zip. If you wish to explore VNA modelling further please contact the author. You may also wish to contact Technical@SiliconDevices.com for an updated copy of the test bench as it is in continuous development because we use similar AC and TRAN testbenches to simulate our IPcells throughout their design cycle.