FM Modulator Testbench SimonH@SiliconDevices.com ******************************* Created 14-04-04 ************************** ******************************* Revised 01-06-06 ************************** *** Netlist written for WinSPICE3 Version 1.05.08 or later. ********************************* Test-Bench ****************************** *************************** Input Drive to Modulator ********************** .PARAM BR=2.4k Xdata Data 0 DataIn *** 2600Hz 2 Pole Low Pass Filter: Llpf Data Dat 61.213m Clpf Dat 0 61.213n Rdmp Dat 0 1e3 X1 (0 Dat FM) FMmod *** Simplified Deviation Meter ******************************************** *** Accurate for 1V equal mark-space ratio sinewave VCOs only! *** Contact us to find out how to alter for more "normal" VCO circuits .... *** For other frequencies, scale capacitor currents to be similar order of *** magnitude as circuitry under test, to preserve accuracy. *************************************************************************** *** Calculate Cint3=Cint2=Cint1=Cint0=(2*PI*fc)^-1 at fc (=125k) *** Values given are for Fc=125k. Remember to enter Vcm to offset Fm: Vcm V 0 1.5 Gint0 int0 0 Fm V -1.4142 Cint0 int0 0 1.2732u IC=0 Rint0 int0 0 1 Gint1 int1 0 int0 0 -1.4142 Cint1 int1 0 1.2732u IC=0 Rint1 int1 0 1 Eint1 g2 0 int1 0 1 Gint2 int2 0 g2 0 -1.4142 Cint2 int2 0 1.2732u IC=0 Rint2 int2 0 1 Gint3 int3 0 int2 0 -1.4142 Cint3 int3 0 1.2732u IC=0 Rint3 int3 0 1 Eint3 g3 0 int3 0 1 *** "Dummy" Resistors to block "node has only one connection" warning: Rfixg2 g2 0 1e12 Rfixg3 g3 0 1e12 *************************** End of Test-Bench ***************************** .OPTIONS METHOD=GEAR ITL5=0 RELTOL=1m ABSTOL=100n VNTOL=100u .control destroy all save all where ************************** Setup Simulation Runs ************************** *** Remember to set RELTOL in .OPTIONS and time step in .TRAN for sufficent *** resolution to get accuracy required ... also VCO requires UIC to set *** initial level and a fine timestep in tran line to minimise amplitude *** droop: tran 20n 8m 20u UIC *** Modulator: * plot v(x1:fd0)+10 v(x1:fd1)+5 v(Fm) ylimit 0 15 * plot v(Fm) *** Demodulator: (remember to remove Vcm from fm) * plot 0.7071*((abs(((v(g2))^2)-(v(g3))*(v(fm)-1.5)))^0.5-1.5) ylimit -0.5 0.5 *** Deviation: enter fc to scale plot 125e3*0.7071*((abs(((v(g2))^2)-(v(g3))*(v(fm)-1.5)))^0.5-1.5) ylimit -50k 50k * plot 125e3*0.7071*((abs(((v(g2))^2)-(v(g3))*(v(fm)-1.5)))^0.5-1.5) ylimit -100 100 *** Scale by fc/(2*df) then offset by 0.5 to see recovered data: * settype notype v(data) * plot (0.8909*((abs(((v(g2))^2)-(v(g3))*(v(fm)-1.5)))^0.5-1.5))*2+0.5 ylimit -0.5 1.5 *** Plot data against MOD(time-delay,sweep) where delay = 1/(2*BR) sweep = 2/BR *** to see eye diagram using: sweep*(atan(tan(PI*(time/sweep-delay/sweep-0.5)))/PI+0.5) * setscale time * settype notype v(data) * plot (v(dat)-1)*2.5+0.5 vs 1m*(atan(tan(PI*(time/1m-0.25m/1m-0.5)))/PI+0.5) plot (0.8909*((abs(((v(g2))^2)-(v(g3))*(v(fm)-1.5)))^0.5-1.5))*2+0.5 vs 1m*(atan(tan(PI*(time/0.83333m-0.20833m/0.83333m-0.5)))/PI+0.5) ylimit -.5 1.5 xlabel Bits *** Plot Modulator Spectrum: linearize *** startf stopf stepf vector *** | | | | * spec 200 250k 200 v(Fm) spec 256 250k 256 v(Fm) plot db(v(Fm)) ylimit -100 20 *************************************************************************** .endc ************************* Sub Circuit Definitions ************************* .SUBCKT FMmod (GND con Iout) ***************************** Modulator Model ***************************** *** Based on modulating an ideal VCO ... .Param Kv=50k Fnom=125k Vm=-1.5 Vcm=1.5 * Based on "Phase Locked Loop Models: Making a VCO" IntuSoft Newsletter * April 1988. Control range is "centred" at 0Hz, so must be offset to Fo * (done by Vo here). Time Domain model only. Use UIC on tran line to set * oscillation level. Set magnitude to minus common mode voltage to minimise * dv/dt start-up transients. Ensure Min timestep is small enough to prevent * magnitude decrease over time. .PARAM PI=3.1415927 * out+ out- order NC1+ NC1- NC2+ NC2- p0+p1f1+p2f2+p3f1^2+p4f1f2+.... G1 Int1 gnd POLY(2) Int2 gnd con1 gnd 0 0 0 0 1 * C1 = 1/(2*PI*abs(Kv)) C1 Int1 gnd 3.183u IC=0 R1 Int1 gnd 1E9 * out+ out- order NC1+ NC1- NC2+ NC2- p0+p1f1+p2f2+p3f1^2+p4f1f2+.... G2 Int2 gnd POLY(2) Int1 gnd con1 gnd 0 0 0 0 -1 * C2 = 1/(2*PI*abs(Kv)) C2 Int2 gnd 3.183u IC=Vm R2 Int2 gnd 1E9 R3 con gnd 1E9 * Vo gnd off {Fnom/abs(Kv)} * Vo places Fnom = 125kHz at Vc=0.5V Vo gnd off 2.0 Econ con1 gnd con off 1 Vcmd gnd cm {Vcm} EoutI Iout gnd Int2 cm 1 EoutQ Qout gnd Int1 cm 1 *** "Dummy" components to block "node has only one connection" warning: RfixCon1 Con1 0 1e12 RfixIout Iout 0 1e12 RfixQout Qout 0 1e12 *************************************************************************** .ENDS FMmod .SUBCKT DataIn (data gnd) ****************************** Data Sig-Gen ******************************* Vdata data gnd DC 0 AC 0 0 PWL( + 0 0 + {1/BR-5n} 0 + {1/BR+5n} 1 + {2/BR-5n} 1 + {2/BR+5n} 1 + {3/BR-5n} 1 + {3/BR+5n} 1 + {4/BR-5n} 1 + {4/BR+5n} 1 + {5/BR-5n} 1 + {5/BR+5n} 0 + {6/BR-5n} 0 + {6/BR+5n} 1 + {7/BR-5n} 1 + {7/BR+5n} 0 + {8/BR-5n} 0 + {8/BR+5n} 1 + {9/BR-5n} 1 + {9/BR+5n} 0 + {10/BR-5n} 0 + {10/BR+5n} 0 + {11/BR-5n} 0 + {11/BR+5n} 0 + {12/BR-5n} 0 + {12/BR+5n} 1 + {13/BR-5n} 1 + {13/BR+5n} 0 + {14/BR-5n} 0 + {14/BR+5n} 0 + {15/BR-5n} 0 + {15/BR+5n} 1 + {16/BR-5n} 1 + {16/BR+5n} 1 + {17/BR-5n} 1 + {17/BR+5n} 1 + {18/BR-5n} 1 + {18/BR+5n} 0 + {19/BR-5n} 0 + {19/BR+5n} 0 + {20/BR-5n} 0 + {20/BR+5n} 0 + {21/BR-5n} 0 + {21/BR+5n} 0 + {22/BR-5n} 0 + {22/BR+5n} 0 + {23/BR-5n} 0 + {23/BR+5n} 1 + {24/BR-5n} 1 + {24/BR+5n} 1 + {25/BR-5n} 1 + {25/BR+5n} 0 + {26/BR-5n} 0 + {26/BR+5n} 0 + {27/BR-5n} 0 + {27/BR+5n} 1 + {28/BR-5n} 1 + {28/BR+5n} 0 + {29/BR-5n} 0 + {29/BR+5n} 1 + {30/BR-5n} 1 + {30/BR+5n} 1 + {31/BR-5n} 1 + {31/BR+5n} 1 + {32/BR-5n} 1 + {32/BR+5n} 0 + {33/BR-5n} 0 + {33/BR+5n} 1 + {34/BR-5n} 1 + {34/BR+5n} 1 + {35/BR-5n} 1 + {35/BR+5n} 1 + {36/BR-5n} 1 + {36/BR+5n} 1 + {37/BR-5n} 1 + {37/BR+5n} 0 + {38/BR-5n} 0 + {38/BR+5n} 1 + {39/BR-5n} 1 + {39/BR+5n} 0 + {40/BR-5n} 0 + {40/BR+5n} 1 + {41/BR-5n} 1 + {41/BR+5n} 0 + {42/BR-5n} 0 + {42/BR+5n} 0 + {43/BR-5n} 0 + {43/BR+5n} 0 + {44/BR-5n} 0 + {44/BR+5n} 1 + {45/BR-5n} 1 + {45/BR+5n} 0 + {46/BR-5n} 0 + {46/BR+5n} 0 + {47/BR-5n} 0 + {47/BR+5n} 1 + {48/BR-5n} 1 + {48/BR+5n} 1 + {49/BR-5n} 1 + {49/BR+5n} 1 + {50/BR-5n} 1 + {50/BR+5n} 0 + {51/BR-5n} 0 + {51/BR+5n} 0 + {52/BR-5n} 0 + {52/BR+5n} 0 + {53/BR-5n} 0 + {53/BR+5n} 0 + {54/BR-5n} 0 + {54/BR+5n} 0 + {55/BR-5n} 0 + {55/BR+5n} 1 + {56/BR-5n} 1 + {56/BR+5n} 1 + {57/BR-5n} 1 + {57/BR+5n} 0 + {58/BR-5n} 0 + {58/BR+5n} 0 + {59/BR-5n} 0 + {59/BR+5n} 1 + {60/BR-5n} 1 + {60/BR+5n} 0 + {61/BR-5n} 0 + {61/BR+5n} 1 + {62/BR-5n} 1 + {62/BR+5n} 1 + {63/BR-5n} 1 + {63/BR+5n} 1 + {64/BR-5n} 1 + ) *************************************************************************** .ENDS DataIn *************************************************************************** *********************** www.silicondevices.com **************************** *************************************************************************** .END